clock generator
英 [klɒk ˈdʒenəreɪtə(r)]
美 [klɑːk ˈdʒenəreɪtər]
时钟脉冲发生器
双语例句
- DRCG Direct Rambus clock generator
直接RAMBUS时钟发生器 - Circuit design of spread-spectrum clock generator based on DP standard
基于DP标准发射端扩频时钟发生器电路设计 - Two Phase Non-Overlap Clock Generator with Independent Pulse Width Adjusting
一种独立调节两相脉宽的不交叠时钟产生电路 - A fast simulation environment has been developed using MATLAB and SIMULINK for behavioral level simulation of spread spectrum clock generator based Fractional-N frequency synthesizers.
提出了一种展频时钟生成的方法，使用MATLAB和SIMULINK开发出了快速模拟基于分数N型频率合成器的展频时钟生成器的环境。 - The sampling clock generator must also have adequate spectral purity.
时钟发生电路固有的抖动应该足够小。 - The on-chip voltage reference and the on-chip clock generator eliminate the need for any external components in capacitive sensor applications.
还集成片内基准电压源和片内时钟发生器，因此在电容传感器应用中无需任何额外外部元件。 - Boosted-high level clock generator
升压高电平时钟发生器 - This commercial integrated chip can be used in the local oscillation circuit, high-accuracy clock generator and so on.
这种商用集成芯片可用于本振合成回路，高精度时钟发生器等。 - A Low-Jitter Clock Generator for HDTV
适用于HDTV的低抖动时钟电路 - New Architecture of Accurate Clock Generator in IC Test System
IC测试系统精密定时器的新结构 - Based on the analysis, a frequency and phase stabilized two-phase sinusoidal power clock generator is proposed, which, while connected to an external reference clock, makes the oscillating circuit in synchronization with the reference clock.
在此基础上，提出了稳定功率时钟频率与相位的功率时钟产生电路，即接入外部参考时钟，使振荡电路与参考时钟同步。 - An Economical Clock Generator& SingleResistor Crystal Oscillator
一种经济的时钟发生器&单阻晶体振荡器 - A 2-GHz CMOS phase-locked loop clock generator research and design
2-GHzCMOS锁相环时钟发生器研究与设计 - The RFID analog front end includes a local oscillator, clock generator, power on reset circuit, matching network and backscatter, rectifier, regulator, and AM demodulator.
该RFID模拟前端包括本地振荡器、时钟产生电路、复位电路、匹配网络和反向散射电路、整流器、稳压器以及AM解调器等。 - High-frequency Clock Generator Based on DDS Hybrid PLL
基于DDS+PLL技术的高频时钟发生器 - Closed-form results are derived, which facilitate efficiency-optimized design of the power clock generator.
为了便于功率时钟的优化设计，推导出了闭式结果。 - In this article the authors introduce a general purpose clock generator based on VXI bus. The clock generator can produce high precision and fine adjustable clock signals.
介绍了一个基于VXI总线的通用时钟发生器，它能产生高精度、可精细调节的时钟信号。 - A Kind of Microcontroller Oscillator and Clock Generator
一种用于微控制器的振荡器及时钟产生电路 - Study and design of an on chip clock generator with high stability
一种高稳定度片内时钟发生器的研究与设计 - A high-speed multi-phase clock generator based on charge-pump phase-locked loop ( PLL) is presented.
介绍了一种基于电荷泵型锁相环的高速多相时钟发生器。 - The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/ D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。 - Design and Simulation of Spread Spectrum Clock Generator
展频时钟生成器的设计与仿真 - A low-jitter clock generator for HDTV is designed with a high-speed phase/ frequency detector, a noise-suppressed charge pump and symmetrical load differential delay cells. Different noise models of the ring oscillator are discussed.
采用高速鉴频鉴相器、抗抖动电荷泵和差分对称负载延迟单元优化结构，综合分析环形振荡器各类噪声模型，设计了一种适用于HDTV的低抖动时钟电路。 - The overall design scheme of signal generation module is put forward. The type of relevant device is determined, and the clock generator, the DDS module, the signal conditioning module and other key part of the design are discussed in detail. 4.
提出了信号产生模块的整体硬件方案，确定了相关器件型号，并对时钟发生器、DDS模块以及信号调理模块等关键部分的设计进行了详细讨论。 - In the digital part, the system timing has been carefully arranged by designing the clock generator. And the rational system timing guarantees the reliability of the system.
在设计数字部分时，通过仔细设计时钟电路产生合理的系统时序，保证了系统的可靠性。 - A two phase non-overlap clock generator with independent pulse width adjusting is designed to let PH2 borrow 12% of the time from PH1, which relaxes the speed specifications for OTA, comparators and DEM.
设计了一种可独立调节两相脉宽的不交叠时钟产生电路，让PH2相借用PH1相12%的时间，以放宽对运放、比较器和DEM单元的速度要求，节省功耗。 - This paper details the working principle and circuit design of DSP clock generator, JTAG interface, rectifier and filter, three-phase inverter bridges, protection circuits and switching power supply, etc. The design of frequency control system is adapted to different types of induction motors within power.
详细介绍了DSP时钟发生器、JTAG接口、整流滤波、三相逆变桥、保护电路、开关电源等工作原理及电路设计；编制了软件功能模块，完成了样机的调试与测试。 - Because of the rapid development of the wireless communication technology, the design and research of the integrated circuits in the related field has gained more and more attention in recent years, There are strict requirements to the clock generator.
近年来由于无线通信技术的飞速发展相关领域的集成电路的设计研究也受到越来越多的关注，从而对时钟系统有了更高的要求。 - The clock generator can be used for arbitrary waveform generators, oscilloscopes, logic analyzers and other digital test instruments.
这套宽带高精度可变时钟发生器的产生方案可用于任意波形发生器、示波器、逻辑分析仪等数字化测试仪器中。 - Delay lock loop circuit, as a kind of high frequency clock generator, is an important research problem of recent CMOS circuit design.
延迟锁相环电路是目前高频时钟产生电路中的重要研究课题之一。